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[Embeded-SCM Develop] memoire_alphabet

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Platform: | Size: 1238 | Author: 秦拣俭 | Hits:

[Other resource] EvsStore

Description: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Platform: | Size: 924 | Author: 杨承凯 | Hits:

[VHDL-FPGA-Verilog] Altera-memory

Description: 这个软件是altera 芯片对SPIflash的一个控制程序，里面读写测试已经通过。-spi flash code for VHDL
Platform: | Size: 125952 | Author: 周明 | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-Mc

Description: vhdl code for memory controller
Platform: | Size: 128000 | Author: JP | Hits:

[VHDL-FPGA-Verilog] module-Temperature

Description: DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据 -DS18B20 Function GND Ground pin, DQ data bus, VDD supply voltage 18B20 There are three forms of memory resources, they are: ROM read-only memory for storing DS18B20ID coding, the top eight single-family is encoded, followed by 48 is the chip serial number only, over the last eight is 56-bit CRC code. DS18B20 total of 64-bit ROM RAM data store, data loss after power-down, a total of 9 bytes, each byte 8-bit, 1, 2 bytes of temperature data converted value information, EEPROM non-volatile volatile memory for storage of long-term need to preserve data, upper and lower temperature alarm and calibration data
Platform: | Size: 9216 | Author: 袁亚楠 | Hits:

[VHDL-FPGA-Verilog] memory

Description: truong trinh thao tac voi memory cua VHDL
Platform: | Size: 53248 | Author: hung | Hits:

[VHDL-FPGA-Verilog] VHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

[VHDL-FPGA-Verilog] Memory-ROMs-RAMs-and-Register-Files

Description: 有关memory的VHDL编码,已经过调制可用，是VHDL的基本编码。-VHDL code for memory.
Platform: | Size: 34816 | Author: 许舒敏 | Hits:

[VHDL-FPGA-Verilog] VHDL-examples

Description: 此文件包含一个VHDL源文件，这足以说明语言的多样性和电源时用来描述不同类型的硬件选择。例子从简单的组合逻辑描述，如一个微处理器和内存相关的行为模式，更复杂的系统。所有的例子可以使用任何符合IEEE VHDL仿真和许多可以模拟 合成使用目前的综合工具。 -This file contains a selection of VHDL source files which serve to illustrate the diversity and power of the language when used to describe various types of hardware. The examples range from simple combinational logic, described in to more complex systems, such as a behavioural model of a microprocessor and associated memory. All of the examples can be simulated using any IEEE compliant VHDL simulator and many can be synthesised using current synthesis tools.
Platform: | Size: 168960 | Author: 东方不败 | Hits:

[FlashMX] sd.vhdl

Description: FLASH MEMORY CONTROLLER TO EMBEDDED PRODUCTS
Platform: | Size: 2048 | Author: manju | Hits:

[Other] Access-memory

Description: 用vhdl写的一个存储器访问程序，下载到FPGA运行通过，有助于了解memory的工作原理。-The vhdl write a memory access program, downloaded to the FPGA to run through the help understand memory works.
Platform: | Size: 215040 | Author: lei liming | Hits:

[VHDL-FPGA-Verilog] VHDL-memory

Description: 存储器的VHDL描述，包括ROM,RAM,FIFO,stack等多种类型-design of memory by VHDL
Platform: | Size: 33792 | Author: zmz | Hits:

[Other Embeded program] VHDL-code-of-ROM-Based-Instruction-Memory

Description: code for 16 bit instruction memory
Platform: | Size: 1024 | Author: tarunsharma | Hits:

[VHDL-FPGA-Verilog] memory

Description: The pipeline SPIN VHDL code (memory part)
Platform: | Size: 1024 | Author: Mehran | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 分块地址产生电路，根据FPGA的要求，按照存储模块分块管理的要求产生电路-Block address generating circuit according to the requirements of FPGA, the memory module according to the requirements of the management block generating circuit
Platform: | Size: 4096 | Author: 王亚鹏 | Hits:

[Education soft system] ReadWrite-RAM-VHDL-source-code

Description: This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic
Platform: | Size: 1024 | Author: ss | Hits:

[Other] vhdl-language-routines-Highlights

Description: vhdl语言例程集锦。文中是经典的英文教程，包含以下内容：Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic Combinational Logic-vhdl language routines highlights. This paper is a classic English tutorial, contains the following: Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic Combinational Logic
Platform: | Size: 216064 | Author: fang | Hits:

[VHDL-FPGA-Verilog] 卷积交织器解交织器设计

Description: 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row, and then read out by column; deinterleaving process is the first data written by the column, then read by line. It is characterized by a simple structure, but the data delay time is long, and the required memory is relatively large.)
Platform: | Size: 753664 | Author: 一个+ | Hits:

[VHDL-FPGA-Verilog] cy7c443

Description: 存储器仿真模型，建立testBench，可对cyc443存储器进行功能仿真。(TestBench memory, can establish simulation model, function simulation of cyc443 memory.)
Platform: | Size: 4096 | Author: cmic589 | Hits:

[VHDL-FPGA-Verilog] ccsuemupc条件跳转(1)

Description: 设计一个模型机，具体设计要求如下： （1）设计指令系统，要求有取数指令、加法指令、跳转指令、停机指令等 （2）设计指令格式、微指令格式 、微程序 、时序电路 、数据通路，完成cpu的设计。 （3）利用模块化设计，分别设计存储器模块、运算器模块、时序电路模块、微程序控制器模块、显示模块等，最后进行系统的顶层设计，完成复杂模型机的设计与实现测试 （4）根据任务，完成主程序的设计，同时把主程序翻译成目标代码，写入主存，仿真下载测试。(Design a model machine, the specific design requirements are as follows: (1) design instruction system, required to have number instructions, addition instructions, jump instructions, downtime instructions and so on (2) Design instruction format, micro-instruction format, micro-program, time series circuit, data path, complete the design of the CPU. (3) The use of modular design, respectively design memory module, operator module, time series circuit module, microcontroller Controller module, display module, etc., and finally carry out the top layer design of the system, complete the design and implementation of complex model machine test (4) According to the task, complete the design of the main program, while translating the main program into the target code, Write the deposit, simulation download test.)
Platform: | Size: 1189888 | Author: 12332122 | Hits:
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